| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u_fifo_port_uart_0|uart_rxfifo |
12 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_fifo_port_uart_0|uart_receiver_u |
4 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_fifo_port_uart_0|uart_transfer_u |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_fifo_port_uart_0|uart_txfifo |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_fifo_port_uart_0|precise_divider_u |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_fifo_port_uart_0 |
11 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u1_ds18b20_dri |
2 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| u_seg_led |
30 |
7 |
0 |
7 |
30 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |